1. Field of the Invention
This invention relates to generating signals, and more particularly to an apparatus and method for controlling the operation of an oscillation circuit such as a phase-locked loop. The invention is also an apparatus and method for controlling power consumption in a system which includes an oscillation circuit.
2. Description of the Related Art
Next-generation communications systems and processing architectures will be expected to meet higher performance requirements than are currently attainable. In order to achieve this goal, various power control methods have been proposed. One method involves altering an operating frequency of the system based on the detection of a certain condition. For example, the system may be driven at a low frequency/low voltage supply to save power and at a high frequency/high voltage supply in high-performance mode.
The operating frequencies of electronic devices are typically generated by a phase-locked loop (PLL). This circuit has proven to be desirable because of its ability to produce a stable output frequency. Because of this property, PLLs are commonly used to generate mixing signals in communications systems, clock signals for controlling the speed and synchronizing the operation of microprocessor systems, and timing signals for transferring data in various data storage applications.
In order to perform the aforementioned power control method, the phase-locked loop must be appropriately controlled. More specifically, the phase-locked loop must be controlled so that its output transitions from one operating frequency to another. For example, when the operating mode of the system demands lower performance, the PLL may be controlled to generate a lower operating frequency than is used for a maximum performance operating mode.
The foregoing methods have proven undesirable because a startup operation must be performed as a necessary prerequisite to changing the output frequency of the phase-locked loop. During this startup operation, the control voltage for setting the output frequency of the PLL is set to a predetermined low value. This causes the output frequency to be proportionately high and in fact not related to the newly desired frequency. In order to achieve the new frequency, the control voltage is increased from its predetermined low value up to a value which will produce the desired output. The time required to increase the control voltage in this manner, however, significantly lengthens the lock time (or re-lock time) of the phase-locked loop, thereby adversely affecting the performance of the host system.